Anuj Vaishnav

Anuj Vaishnav, PhD

Team Lead at Bloomberg · Electronic Trading

I build and optimise computer systems. Today that means high-performance distributed systems for fixed income trading. Before that, latency engineering at AMD, a startup, and a PhD at the University of Manchester on resource management and FPGA virtualisation, where I designed FOS, an operating system for FPGAs (watch the demo).

Across FPGAs, RTL, compilers, networking and distributed systems I keep meeting the same problem: the hard part is not solving the bottleneck, it is finding which one matters. Lately I have been writing about whether AI agents can learn to do the same.

Get in touch GitHub Scholar LinkedIn

Writing All posts →

· 9 min read

State Is Not Context: What Long-Horizon Agents Need to Preserve

A long agent run accumulates records, not a current position. The harder capability is knowing what the past has made true and what has ceased to be.

Read the essay →
· 12 min read

The Geometry of Reachable Futures

A long-horizon agent needs more than the current state and the goal. It also needs to represent how each choice changes the futures that remain reachable.

Read the essay →

Selected work

FOS — FPGA Operating System

Traditional or multi-tenant FPGA use, on a modular build flow and resource-elastic scheduler. Demoed live at FPL 2019.

Modular FPGA development flow

Every component swappable and agnostic to EDA tool version, hardware and software layer.

Heterogeneous resource elasticity

Change allocation across FPGA and CPU transparently: compute units, partitioning, accelerator and device selection.

Live migration for FPGA accelerators

Move an OpenCL accelerator between FPGAs with low overhead. Best paper nominee, FPT 2018.

Experience

Publications Google Scholar →

2020
  • A. Vaishnav, et al.. FOS: A Modular FPGA Operating System for Dynamic Workloads. ACM TRETS. Read
2019
  • K. Manev*, A. Vaishnav*, D. Koch. Unexpected Diversity: Quantitative Memory Analysis for Zynq UltraScale+ Systems. FPT, Tianjin. Read
  • A. Vaishnav, et al.. Heterogeneous Resource-Elastic Scheduling for CPU+FPGA Architectures. 10th HEART, Nagasaki. Read
  • A. Vaishnav, et al.. The FOS (FPGA Operating System) Demo. 29th FPL, Barcelona. Read
  • K.D. Pham, K. Paraskevas, A. Vaishnav, et al.. ZUCL 2.0: Virtualised Memory and Communication for ZYNQ UltraScale+ FPGAs. 6th FSP, Barcelona. Read
  • K. Manev, A. Vaishnav, et al.. Scalable Filtering Modules for Database Acceleration on FPGAs. 10th HEART, Nagasaki. Read
  • A. Vaishnav, et al.. Heterogeneous Resource-Elastic Management for FPGAs: Concepts, Theory and Implementation. Preprint. Read
2018
  • A. Vaishnav, et al.. Live Migration for OpenCL FPGA Accelerators. FPT, Naha. Best paper nominee Read
  • A. Vaishnav, et al.. Resource Elastic Virtualization for FPGAs using OpenCL. 28th FPL, Dublin. Read
  • A. Vaishnav, et al.. A Survey on FPGA Virtualization. 28th FPL, Dublin. Read
  • K.D. Pham, A. Vaishnav, et al.. ZUCL: A ZYNQ UltraScale+ Framework for OpenCL HLS Applications. 5th FSP. Read
  • K.D. Pham, E. Horta, D. Koch, A. Vaishnav, T. Kuhn. IPRDF: An Isolated Partial Reconfiguration Design Flow for Xilinx FPGAs. 12th MCSoC. Read
2017
  • A. Vaishnav, et al.. A Security Library for FPGA Interlays. 27th FPL, Ghent. Read

* denotes joint first authorship.

Talks

Honours

Get in touch

Happy to talk about systems performance, hardware acceleration, or where AI agents are heading. Away from a screen: cycling, long walks, chess, Age of Empires 2, and phone-camera photography.

dranujvaishnav@gmail.com LinkedIn ResearchGate GitHub